1. Field of the Invention
This disclosure relates to a logic device and a method of fabricating the same and more particularly, to a logic device having a vertically extending metal-insulator-metal capacitor between interconnect layers and a method of fabricating the same.
2. Description of the Related Art
Generally, a capacitor of a logic device is used as an impedance element. The capacitor used as an impedance element must be linear in its response characteristics. Therefore, a metal-insulator-metal (MIM) capacitor is normally used in the logic device instead of a poly-insulator-poly (PIP) capacitor which exhibits non-linear response characteristics due to charge depletion.
Chemical mechanical polishing (CMP) smooths relatively significant variations in height of the different components to a planar surface. Smoothing or planarizing the variable-height topology to a planar surface allows the typical lithographic semiconductor fabrication techniques to be used to form considerably more layers than were previously possible in IC construction. That is, even though many layers are formed in a stack, the stacked layers can be patterned by using photolithography processes because the surface of the layers is planarized. Thus, CMP technology allows more circuitry to be incorporated on a single substrate in a single IC. As a result, with the employment of CMP technology in the fabrication process of semiconductor devices, a large number of interconnections (referred to as “interconnect layers”) can be layered in a stack.
The interconnect layers are insulated by an interlayer insulating layer. If a capacitor is formed inside the interlayer insulating layer between the interconnect layers, it does not consume the space on the semiconductor substrate, and it is possible to provide a capacitor suitable for a logic device and save space.
With the high-integration of the logic device, there is required a capacitor capable of providing a high capacitance in a unit surface area on a semiconductor substrate.
An MIM capacitor between interconnect layers for providing high capacitance in a unit surface area is disclosed in U.S. Pat. No. 6,057,571, entitled, “High aspect ratio, metal-to-metal, linear capacitor for an integrated circuit,” to Miller, et. al.
In the capacitor disclosed by Miller, upper and lower metal plates vertically extend between interconnect layers. Thus, the capacitor has a relatively high aspect ratio and a relatively large value of capacitance in consideration of the surface area it consumes.
However, in the capacitor disclosed by Miller, the thickness of an insulating layer interposed between the brim of the lower metal plate and the upper plate is not greater than the deposition thickness of a capacitor dielectric layer. Because the brim of the lower metal plate is caught by an electric field more than other locations, a leakage current is often generated, unless the thickness of the capacitor dielectric layer is high.
Further, the method of fabricating a capacitor disclosed by Miller includes forming lower interconnect layers. An interlayer insulating layer is formed on the semiconductor substrate having the lower interconnect layers formed thereon, and the interlayer insulating layer is patterned so as to form a capacitor hole. Then, a lower U-shaped metal plate is formed inside the capacitor hole. Then, a capacitor dielectric layer is formed on the semiconductor substrate having the lower U-shaped metal plate formed thereon. Then, by using a typical photolithography technology, the capacitor dielectric layer and the interlayer insulating layer are patterned so as to form a via hole. The via hole exposes the lower interconnect layer. An upper plate is formed on the overall surface of the semiconductor substrate having the via hole formed thereon. The upper plate covers the top surface of the capacitor dielectric layer. Further, the upper plate extends to cover the side walls of the via hole, and the extended upper plate is connected electrically to the exposed lower interconnect layer.
According to the method, after the capacitor dielectric layer is formed, the via hole is formed using a photolithography technology. Thus, it is necessary to form a photoresist layer on the capacitor dielectric layer. Since the photoresist layer includes organic components such as hydrogen or carbon, it can contaminate the dielectric layer.
Further, after the lower interconnect layer is exposed, it is necessary to remove a native oxide layer on the top surface of the exposed lower interconnect layer in order to form the upper plate. Thus, after the via hole is formed, a cleaning process of the oxide layer is required before the upper plate is formed. However, the cleaning process of the oxide layer may remove a part of the capacitor dielectric layer, and thereby damage the capacitor dielectric layer. As a result, the thickness of the capacitor dielectric layer interposed between the brim of the lower plate and the upper plate becomes much thinner, so that the leakage current characteristics may be degraded.